1. Field of the Invention
The invention generally relates to integrated circuits for use in computer systems and in particular to circuitry for use in inputting and decoding address signals within a synchronous integrated circuit having input buffers, decode units, sample and hold registers and the like.
2. Description of Related Art
State of the art integrated circuits for use in computer systems, such as cache-RAM integrated circuits and the like, require the fastest possible processing speeds and clock rates. Accordingly, it is desirable to gain speed improvements within all portions of the integrated circuit, particularly within input/output signal transmission paths. Within a cache-RAM integrated circuit, or similar synchronous integrated circuits, one component of the circuit which could benefit from speed improvement is the input path for address signals wherein input address signals are sampled and held in a clocked input register then decoded. FIG. 1 illustrates a conventional address input path circuit 10 wherein address signals received along an input line 12 are stored in a register 14 then decoded by pre-decode and mid-decode units 16 and 18, respectively. Additional decode units, not shown, may additionally be employed. Register 14 is clocked by a clock signal received along input clock line 20 by an input buffer 22. Prior to triggering register 14, the input clock signal is passed through a pulse generator 24 which generates a pulse of predetermined width on each rising edge of the input clock signal for use elsewhere within the integrated circuit containing address input path circuit 10. Additionally, the clock signal is passed through a control logic unit 26 which, depending upon the implementation, may control the clock signal based upon control signals received elsewhere in the circuit.
For proper operation of register 14, the clock signal must be received by the register during a time period during which the address signal received along line 12 is available to the register. In order to have margin for set-up time, the clock signal should be received by the register as late as possible. In order to have margin for hold time, the clock signal should be received by the register as early as possible. In order to respect both set-up and hold times, the clock signal is required to be received by the register within a given time window relative to the reception of the address signal at the input of the register. Preferably, the clock signal is received by the register at about a midway time during this time window, to provide substantially equal set-up and hold time margins for the address signal. However, passing the clock signal through pulse generator 24 and control logic 26 causes a certain amount of delay which may prevent the clock signal from reaching register 14 in a timely manner. Accordingly, a delay unit 28 is provided along the input path of the address signal prior to register 14 to delay the address signal by an amount sufficient to ensure that the address signal is available to the register during the time period in which the clock signal is received by the register.
Ideally, the set-up and hold time for register 14 is kept to a minimum. In practice, however, it is often necessary to provide a fairly long set-up and hold time period to account for any timing differences or skew between availability of the address signals and receipt of the clock signal. If the set-up and hold time is too short, then any significant skew may cause the clock signal to be received either before or after the set-up and hold period, resulting in loss of the input address data.
One source of timing skew occurs as a result of process variations in the fabrication of input buffers 13 and 22. FIG. 2 illustrates an exemplary conventional input buffer cell 30 subject to process variations. Input buffers 13 and 22 of FIG. 1 may be composed of a number of input buffer cells with one cell per individual input line. Buffer cell 30 includes a first inverter stage 32 and a second inverter stage 34. Inverter stage 32 includes a PMOS device 36 and NMOS 38. Although not shown, inverter stage 34 may incorporate a similar device arrangement. Collectively, the pair of inverters of the input buffer cell operate to receive, and perhaps modify, an input signal. The input buffer cell may, for example, modify the voltage range of the input signal to range from between 0 to 3 volts to between 0 to 5 volts. Although the input buffer cell of FIG. 2 may adequately operate to achieve those results, the use of both PMOS and NMOS devices results in timing skews as a result of process variations between the PMOS and NMOS devices. As such, signals sent simultaneously through two different input buffer cells configured as in FIG. 2 will likely be output by the input buffers with a slight timing difference or skew. This skew is especially noticeable when one input is rising and another input is falling. Hence, if implemented using the buffer cells of FIG. 2, the input buffers of FIG. 1 will likely output their respective address or clock signals subject to a timing skew affecting the receipt of the signals by the register. To compensate for the possibility of such a timing skew, the overall set-up and hold time of the register must be set to a somewhat longer time period than would otherwise be desirable, resulting in overall poorer timing specifications for the entire integrated circuit containing the register.
FIG. 3 illustrates one possible solution for eliminating the process skew problems in the configuration of FIG. 2. More specifically, FIG. 3 illustrates an input buffer cell 40 having a pair of inverter stages 42 and 44 with individual device components of inverter stage 42 separately shown. (Inverter stage 44 may have a similar configuration to the first inverter stage of FIG. 2.) As can be seen, inverter stage 42 includes a pair of NMOS devices 46 and 48 with a gate of device 46 connected to a power supply and a gate of device 48 connected to the input. NMOS device 46 is smaller in size and strength than NMOS device 48. With this configuration, timing skew problems resulting from process variations between PMOS and NMOS devices are avoided because only NMOS devices are employed. Thus, by configuring the input buffers of FIG. 1 using the NMOS-only cell configuration of FIG. 3, timing skew as a result of process variations between the address signals and the clock signals is reduced thereby allowing a more precise set-up and hold time to be specified for the register. Unfortunately, although the NMOS configuration of FIG. 3 helps eliminate process skew problems, significant power consumption occurs as a result of leakage current within the input buffer cell. More specifically, by employing two NMOS devices in series between a power source and ground, a DC path is provided, thereby consuming significant power. Accordingly, relatively large current flows through the first inverter stage 42, particularly, when the input is held high. Additionally, some current passes through the second inverter stage 44 when the input is held low. The current drawn through the first inverter is caused by the two NMOS devices both being in an active state when the input is held high. The current flow through the second inverter 44 is caused by a voltage drop across NMOS pull-up device 46 when the input is held low. This voltage drop results in a voltage level at the input of the second inverter 44 which is not high enough to completely turn off the PMOS device (not separately shown) of the second inverter resulting in further leakage current.
Hence, the input buffer configuration of FIG. 3 reduces timing skew as a result of process variations but does so at the expense of consuming significantly greater current. FIG. 4 illustrates yet another configuration for an input buffer cell which also reduces process skew variations and provides improved power consumption, yet which is also not optimal. More specifically, FIG. 4 illustrates an input buffer cell 50 having a first inverter stage 52 and a second inverter stage 54. Again, the second inverter stage may be simple PMOS/NMOS inverter such as illustrated in FIG. 2. Inverter stage 52 includes a pair of NMOS devices 56 and 58 and a PMOS device 60. NMOS devices 56 and 58 are connected similarly to corresponding NMOS devices of the input buffer cell of FIG. 3 with NMOS device 56 being smaller than NMOS device 58. However, whereas the small NMOS device 46 of FIG. 3 is connected directly to a power supply, the drain of the NMOS device 56 is connected to the power supply through PMOS device 60. A gate of device 60 is connected to the input line. By providing PMOS device 60 connected as shown, power consumption is substantially eliminated when the input is held high. However, when the input is held low, some current leakage still occurs within the second inverter stage for the same reasons as described with reference to the input buffer cell of FIG. 3. Hence, the addition of the PMOS device within the first stage only partially eliminates the current leakage problem. It should be noted that the presence of the PMOS device in the first stage does not result in process skew because transmission of the input signal through the first inverter stage to the second inverter stage is controlled by the pair of NMOS devices.
Thus, it would be desirable to provide an improved method for eliminating process skew between input buffer cells, such as those employed within the address signal input path of FIG. 1, yet which does so with little or no resulting leakage current. The provision of such an improved input buffer cell would allow for a reduction in the required set-up and hold times for the input register without unduly increasing power consumption.
Referring again to FIG. 1, a second area in which timing improvement can be gained lies within the positioning of decode units 16 and 18. As shown in FIG. 1, the decode units are positioned after the register resulting in additional timing delays beyond those occurring during signal transmission prior to the register. One proposed solution is illustrated in FIG. 5. The address input path arrangement of FIG. 5 is similar to that of FIG. 1 and like components are identified by like reference numerals, incremented by 100. The arrangement of FIG. 5 is not necessarily prior art to the present invention. In the arrangement of FIG. 5, the decode units prior to the register are arranged to eliminate delay occurring following the register. Moreover, no significant additional delay occurs prior to the register. Rather, the timing delay artificially added by way of delay unit 128 is reduced to account for any additional delay caused by the presence of decode units 116 and 118. Hence, whereas delay unit 28 of FIG. 1 provides sufficient delay to account for clock signal delays through pulse generator 24 and control logic 26, delay unit 128 of FIG. 5 provides only sufficient delay to account for any remaining timing differences between address signals passed through decode units 116 and 118 and clock signals passed through pulse generator 124 and control logic 126.
Hence, timing delays occurring prior to the registering of the address signal are not substantially increased, yet timing delays occurring after the register are reduced significantly by not requiring decode operations to be performed subsequent to registering. Although the arrangement of FIG. 5 provides significant overall timing improvement, further improvement can be gained. In particular, the presence of the decode units prior to the register results in some additional skew which, if not compensated for, could require an increase in the set-up and hold times for the register thereby forfeiting some of the advantage gained by repositioning the decode units. More specifically, timing skew may occur through the decode units between two address signals composed of differing numbers of zeros and ones. The address input path must accommodate any possible address input signals ranging from those containing all zeros to those containing all ones. Hence, any timing differences between transmission of different address signals must be compensated for by providing a correspondingly longer set-up and hold period, resulting in the aforementioned degradation in the overall timing advantages of the address input path of FIG. 5.
The timing skew occurring as a result of differences in address input signals will now be described more fully with reference to FIG. 6. Decode units, such as pre-decode unit 116 and mid-decode unit 118 of FIG. 5, are typically configured with sets of NAND gates or NOR gates for performing logic operations to achieve decoding of a multiple bit binary input address signal. FIG. 6 illustrates a single conventional CMOS NAND gate receiving two input address bits along lines 132 and 134, respectively. NAND gate 130 includes a pair of PMOS devices 136 and 138 connected in parallel to a power source and a pair of NMOS devices 140 and 142 connected in a series between a ground and a node interconnecting drains of the pair of PMOS devices. Gates of PMOS devices 136 and 138 are connected, respectively, to input lines 132 and 134. An output line 144 is connected to the node interconnecting the two PMOS devices and NMOS device 140.
The amount of time required for NAND gate 130 to input signals and generate an output signal depends whether the input signals are both zero, both one, or a combination of the two. More specifically, when an input signal along line 132 transitions from a high state to a low state while an input signal along line 134 is held high, the output line is pulled up through only one of the two PMOS devices, namely, PMOS device 136. On the other hand, if both inputs transition simultaneously from high to low, the output is pulled up by both PMOS devices. Two PMOS devices pulling up the output line, rather than only one, results in faster propagation of the signals through the NAND gate. Hence, timing skew occurs between two NAND gates receiving different input signals. Although not separately shown, similar skew problems occur between two NOR gates receiving different input signals.
For a practical implementation of a pair of pre-decode and mid-decode units, hundreds of NAND gates and NOR gates may be employed to collectively decode an input address signal composed of, for example, 32 or 64 bits. The collective difference in timing delays among the many levels of NAND gates and NOR gates can be significant requiring the set up and hold time for register to be increased to accommodate the resulting timing uncertainty in the availability of the address signal to thereby ensure that clock signal is received while the address signal is actually available.
Accordingly, it would be desirable to provide an improved logic gate, such as a NAND gate or NOR gate, for use in a decode unit to substantially eliminate timing skew between the output of signals corresponding to different input signals to thereby achieve overall improved timing performance.